CVD_Andes ver 2.01 23/Sep/2014

New CVD_Andes version 2.01 has been released.

 

 

<The Key Facts of CVD_Andes v2.01>

 

1. Added

 - Support new cores
   ; N705, N801, N968, N1068, N1337 V2:N1233

 - Support new instruction set
   ; V3,V3m instruction set

 - Support multi core debugging
   ; debug two or many cores which chained into one jtag chain

 - Support automatic PA->VM address translation

 - Added System register files for new cores(N705,N801, N968, N1068, N1337 V2:N1233)

 - General Purpose Register number effected by Reduced Register Configuration setting

 - SWBP works even the code is in cache

 - Single step implemented with hardware single step which supported by EDM

 - CVD status reflected by real target system status

 

2. Fixed Bug

 - Fixed step over bug

 - Fixed call stack bug

 - Fixed system register index mismatch bug

 - Fixed variable read/write issue on debugging linux application

 

For more information, please refer to CVD_v2.01_ReleaseNote.pdf and CVD_v2.00 manuals in CVD install directory. (\JnDTech\CVI\CVD_ANDES)

 

Thank you.